1. Field of the Invention
This invention relates to a semiconductor memory device with electrically rewritable and non-volatile memory cells, i.e., EEPROM, specifically to a technology of reducing the error-write rate of a NAND-type flash memory.
2. Description of the Related Art
A NAND-type flash memory is known as one of electrically rewritable and highly integrative non-volatile semiconductor memories (EEPROMs). In the NAND-type flash memory, multiple memory cells are connected in series in such a manner that adjacent two memory cells share a source/drain diffusion layer to constitute a NAND cell unit. The both ends of the NAND cell unit are coupled to a bit line and a source line via select transistors, respectively. By use of such a NAND cell unit configuration, it becomes possible to make the unit cell area smaller than a NOR-type flash memory, and achieve a large capacity.
A memory cell of the NAND-type flash memory has a floating gate formed on a semiconductor substrate with a tunnel insulator film interposed therebetween and a control gate stacked above the floating gate with a gate-insulating film interposed therebetween, and stores data in a non-volatile manner in accordance with the charge storage state in the floating gate. Explaining in detail, a binary data storage scheme is used as follows: a high threshold voltage state, which is obtained by injecting electrons into the floating gate, serves as data “0” while a low threshold voltage state, which is obtained by discharging electrons in the floating gate, serves as data “1”. Recently, multi-level (e.g., four-level) data storage scheme is used by dividing a write threshold distribution into two or more distributions.
Assuming that all memory cells (or the half) arranged along a selected word line is dealt with a page, data program (or write) of the NAND-type flash memory is performed page by page. In detail, data program is performed as follows: apply program voltage Vpgm to a selected word line, and inject electrons into the floating gate by FN tunneling from the cell channel. At this program time, a NAND cell channel will be controlled in potential via a bit line in accordance with program data “0” or “1” supplied to the bit line.
Explaining in detail, in case of “0” program, a corresponding bit line is set at Vss, and this is transferred to a selected cell's channel via a select gate transistor, which is turned on. In this case, a large electric field is applied between the floating gate and the cell channel, so that electrons are injected into the floating gate. By contrast, in case of “1” program, a corresponding bit line is applied with Vdd, and a selected cell's channel is charged up to Vdd-Vth (Vth: threshold voltage of the select gate transistor) to be set in a floating state. In this case, the cell's channel is boosted by capacitive coupling from the selected word line with Vpgm applied, so that electron injection into the floating gate will be inhibited.
If the cell's channel boost in a “1” program cell (i.e., program-inhibited cell) with Vpgm applied is insufficient, electrons are injected into the floating gate, and undesirable threshold variation will occur. Non-selected word lines are usually applied with program pass voltage (medium voltage) Vm that is lower than Vpgm. If the cell's channel boost is insufficient in these non-selected cells under the non-selected word lines, erroneous program will occur.
In the prior arts, there have been provided some channel voltage control schemes used for suppressing the erroneous program mode in “1” program cells and non-selected cells at a program time as follows:
(1) Self-boost (SB) scheme - - - at a “1” write time, the whole channels in a NAND-cell unit are set in a floating state, and boosted by capacitive coupling from a selected word line.
(2) Local self-boost (LSB) scheme - - - at a “1” write time, a selected cell's channel is boosted in such a state that the selected cell's channel is isolated from the remaining channels.
(3) Erase area self-boost (EASB) scheme - - - assuming that cells are programmed in order from the source line side, unwritten cell area including a currently selected cell and already written cell area are insulated from each other, and boosted independently.
Even if these channel voltage control schemes are adapted, there will be remained such a problem that erroneous program occurs in a cell adjacent to a select gate transistor (specifically, a select gate transistor on the source line side) when the NAND-type flash memory is miniaturized more. At a data program time, the select gate transistor disposed on the source line side is kept off with gate voltage 0V applied. At this time, if a cell adjacent to the select gate transistor is “1” program one (i.e., program-inhibited cell) with program voltage Vpgm applied, gate induced drain leakage (GIDL) current flows at the drain edge of the select gate transistor, and erroneous program occurs in the cell adjacent to the select gate transistor as s result of electron injection into the floating gate due to the GIDL current.
It is known that in case the cell adjacent to the select gate transistor is applied with program pass voltage Vm(<Vpgm), erroneous program occurs as similar to the above described case. Further, it is also known that there is generated an erroneous program in a cell adjacent to the bit line side select gate transistor as described above.
To suppress the above-described erroneous program due to the GIDL current, some methods have been provided as follows: a method for suppressing the GIDL current at the drain edge of the select gate transistor (for example, improving the channel profile); and another method for suppressing the hot electron injection due to GIDL current (for example, widening the distance between the select gate transistor and the memory cell). However, these dealing methods lose the effectiveness as the minimum feature device size becomes more less.
It is one effective method for suppressing the erroneous program to dispose a dummy cell neighboring to a select gate transistor, which is not used for storing data (for example, see JP-A-2006-186359).
Further, it is known a so-called soft-program scheme used for dissolving an over-erase state in erase cells, which have been collectively erased (for example, refer to JP-A-2006-059532). This scheme is important for preventing the cell data from being varied due to capacitive coupling between adjacent cells because it is possible to narrow the data threshold distributions as a whole. Specifically, it becomes important for improving the erroneous program of a miniaturized NAND-type flash memory (specifically, in a multi-level NAND-type flash memory).
However, even if these dummy cell scheme or soft-program scheme is used, there will be remained the erroneous write problem due to the GIDL current in a NAND-type flash memory with a design rule of 60 nm or less.